MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 118

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Cache
If the desired address is mapped into the cache memory, the output of the storage array is driven
onto the ColdFire core's local data bus, thereby completing the access in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are
loaded into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide
temporary storage for the last line fetched in response to a cache miss. With each fetch, the
contents of the associated line fill buffer are examined. Thus, each fetch address examines both
the tag memory array and the associated line fill buffer to see if the desired address is mapped into
either hardware resource. A cache hit in either the memory array or the associated line-fill buffer
is serviced in a single cycle. Because the line fill buffer maintains valid bits on a longword basis,
hits in the buffer can be serviced immediately without waiting for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill buffer, the
cache initiates the required external fetch operation. In most situations, this is a 16-byte line-sized
burst reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is
released after the initial access of a miss. Thus, the cache or the SRAM module can service
subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer.
MCF5271 Reference Manual, Rev. 2
5-2
Freescale Semiconductor