MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 166

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Power Management
8.2.1.1
Implementation of low-power stop mode and exit from a low-power mode via an interrupt require
communication between the CPU and logic associated with the interrupt controller. The LPICR is
an 8-bit register that enables entry into low-power stop mode, and includes the setting of the
interrupt level needed to exit a low-power mode.
The following is the sequence of operations needed to enable this functionality:
8-2
1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired
2. At the appropriate time, the processor executes the privileged STOP instruction. Once the
3. The entry into a low-power mode is processed by the low-power mode control logic, and
4. After entering the low-power mode, the interrupt controller enables a combinational logic
5. Once an appropriately high interrupt request level arrives, the interrupt controller signals
6. The low-power mode control logic senses the request signal and re-enables the appropriate
7. With the processor clocks enabled, the core processes the pending interrupt request.
low-power mode) and loading the appropriate interrupt priority level.
processor has stopped execution, it asserts a specific Processor Status (PST) encoding.
Issuing the STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to
enter stop mode.
the appropriate clocks (usually those related to the high-speed processor core) are
disabled.
path which evaluates any unmasked interrupt requests. The device waits for an event to
generate an interrupt request with a priority level greater than the value programmed in
LPICR[XLPM_IPL[2:0]].
its presence, and the SCM responds by asserting the request to exit low-power mode.
clocks.
Low-Power Interrupt Control Register (LPICR)
The setting of the low-power mode select (LPMD) field in the power
management module’s low-power control register (LPCR) determines
which low-power mode the device enters when a STOP instruction is
issued.
If this field is set to enter stop mode, then the ENBSTOP bit in the
LPICR must also be set.
Only a fixed (external) interrupt can bring a device out of stop mode.
To exit from other low-power modes, such as doze or wait, either fixed
or programmable interrupts may be used; however, the module
generating the interrupt must be enabled in that particular low-power
mode.
MCF5271 Reference Manual, Rev. 2
NOTE
NOTE
Freescale Semiconductor