MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 57

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
2.3 Signal Primary Functions
2.3.1 Reset Signals
Table 2-2
Freescale Semiconductor
Reset In
Reset Out
Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name
describes signals that are used to either reset the chip or as a reset indication.
1
2
Signal Name
PLL_TEST
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup
enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS,
PSDRAM.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO
module is not responsible for assigning these pins.
VDDPLL
VSSPLL
OVDD
TEST
VDD
VSS
RESET
RSTOUT
Abbreviation
GPIO
MCF5271 Reference Manual, Rev. 2
Primary reset input to the device. Asserting RESET immediately
resets the CPU and peripherals.
Driven low for 128 CPU clocks when the soft reset bit of the system
configuration register (SCR[SOFTRST]) is set. It is driven low for 32K
CPU clocks when the software watchdog timer times out or when a
low input level is applied to RESET.
Table 2-2. Reset Signals
Alternate
1
Power Supplies
Alternate
Test
2
Dir.
1
I
I
I
I
I
I
I
Function
55, 69, 81, 94,
17, 31, 40, 54,
67, 80, 88, 93,
105, 114, 128,
104, 113, 127,
137, 144, 160
1, 18, 32, 41,
16, 53, 103
MCF5270
MCF5271
160 QFP
138, 145
19
87
84
E9, F6, F8, F10,
F7, F9, G6, G8,
J8, J10, K5, K6,
G7, G9, H6, J5,
D6, F11, G4, L4
H7, H8, H9, J6,
J7, J9, K7, P1,
196 MAPBGA
E5, E7, E10,
A1, A14, E6,
MCF5270
MCF5271
M13
P14
L14
F5
K8
Signal Primary Functions
I/O
O
I
2-7

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