MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 610

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Base Address: IPSBAR
Base Address: IPSBAR
0x10_003C
0x10_004C
0x10_0030
0x10_0034
0x10_0038
0x10_0040
0x10_0044
0x10_0048
0x10_0050
0x10_0054
Offset
1
2
3
0x11_000C
0x11_0004
0x11_0008
0x11_0010
See
Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
Offset
Chapter 8, “Power
12-16
12-18
12-27
Page
Page
9-4
8-3
9-5
9-7
—
—
Management,” for a description of the LPCR. It is shown here only to warn against accidental writes to this register.
Port Clear Output Data Registers
Drive Strength Control Registers
Pin Assignment Registers
Table A-14. GPIO (Ports) Memory Map (Continued)
Register Description
Reset Configuration Register
Low-Power Control Register
Chip Configuration Register
Chip Identification Register
Register Description
Table A-15. CCM Memory Map
PCLRR_UARTH
PCLRR_ADDR
PCLRR_ETPU
DSCR_QSPI
PCLRR_BS
DSCR_EIM
PAR_AD
PAR_BS
[31:24]
[31:24]
PAR_TIMER
PAR_UART
RCON
CCR
PCLRR_DATAH
PCLRR_UARTL
DSCR_TIMER
DSCR_ETPU
PCLRR_CS
PAR_CS
[23:16]
[23:16]
Unimplemented
Reserved
PCLRR_SDRAM
PCLRR_DATAL
DSCR_FECI2C
PCLRR_QSPI
PAR_SDRAM
PAR_ETPU
PAR_QSPI
2
[15:8]
[15:8]
3
PAR_BUSCTL
LPCR
CIR
1
PCLRR_BUSCTL
PCLRR_FECI2C
PCLRR_TIMER
PAR_FECI2C
DSCR_UART
[7:0]
[7:0]