MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 415

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

22.2.9 DMA Timer Reference Registers (DTRRn)
Each DTRRn, shown in
free-running timer counter (DTCNn) as part of the output-compare function. The reference value
is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be
incremented again. Thus, the reference register is matched after DTRRn+1 time intervals.
Freescale Semiconductor
Bits
7–2
1
0
Name
REF
CAP
—
Reserved, should be cleared.
Output reference event. The counter value, DTCNn, equals the reference value, DTRRn.
Writing a one to REF clears the event condition. Writing a zero has no effect.
Capture event. The counter value has been latched into DTCRn. Writing a one to CAP
clears the event condition. Writing a zero has no effect.
Figure
Table 22-4. DTERn Field Descriptions
CAP
0
1
1
1
1
1
1
1
1
22-5, contains the reference value compared with the respective
REF
0
1
1
1
1
MCF5271 Reference Manual, Rev. 2
DTMRn[CE]
00
00
01
01
10
10
11
11
DTMRn[ORRI]
X
X
0
0
1
1
[DMAEN]
DTXMRn
X
0
1
0
1
0
1
0
1
DTXMRn[DMAEN]
Description
Capture on falling edge & trigger interrupt
Capture on rising edge & trigger interrupt
Capture on any edge & trigger interrupt
Capture on falling edge & trigger DMA
Capture on rising edge & trigger DMA
X
Capture on any edge & trigger DMA
0
1
0
1
Disable capture event output
Disable capture event output
Interrupt request asserted
No event
DMA request asserted
No request asserted
No request asserted
Memory Map/Register Definition
No event
22-7