MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 264

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Interrupt Controller Modules
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up
signal to exit from the low-power stop mode. This special mode of operation works as follows:
For more information, see
13-16
• First, LPICR[XLPM_IPL] is loaded with the mask level that will be specified while the
• Second, the processor executes a STOP instruction which places it in stop mode. Once the
core is in stop mode. LPICR[ENBSTOP] must be set to enable this mode of operation.
processor is stopped, each interrupt controller enables a special logic path which evaluates
the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked
storage elements. If an active interrupt request is asserted and the resulting interrupt level
is greater than the mask value contained in LPICR[XLPM_IPL], then each interrupt
controller asserts the wake-up output signal, which is routed to the SCM where it is
combined with the wakeup signals from the other interrupt controller and then to the PLL
module to re-enable the device’s clock trees and resume processing.
The wakeup mask level taken from LPICR[XLPM_IPL] is adjusted
by hardware to allow a level 7 IRQ to generate a wakeup. That is, the
wakeup mask value used by the interrupt controller must be in the
range of 0–6.
Section 8.2.1.1, “Low-Power Interrupt Control Register
MCF5271 Reference Manual, Rev. 2
NOTE
Freescale Semiconductor
(LPICR).”