MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 426

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Queued Serial Peripheral Interface (QSPI) Module
Outbound data must be written to transmit RAM in a right-justified format. The unused bits are
ignored. The QSPI copies the data to its data serializer (shift register) for transmission. The data
is transmitted most significant bit first and remains in transmit RAM until overwritten by the user.
23.2.1.3 Command RAM
The CPU writes one byte of control information to this segment for each QSPI command to be
executed. Command RAM, referred to as QCR0–15, is write-only memory from a user’s
perspective.
Command RAM consists of 16 bytes with each byte divided into two fields. The peripheral chip
select field controls the QSPI_CS signal levels for the transfer. The command control field
provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in
QWR[NEWQP] through the address in QWR[ENDQP].
The QSPI executes a queue of commands defined by the control bits in each command RAM entry
which sequence the following actions:
Before any data transfers begin, control data must be written to the command RAM, and any
out-bound data must be written to transmit RAM. Also, the queue pointers must be initialized to
the first and last entries in the command queue.
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity
are controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which
QSPI_CLK edge is used to drive outgoing data and to latch incoming data.
23.2.2 Baud Rate Selection
The maximum QSPI clock frequency is one-fourth the clock frequency of the internal bus clock.
Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler
to derive the QSPI_CLK rate from the internal bus clock divided by two.
A baud rate value of zero turns off the QSPI_CLK.
The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the
following expression:
23-6
• Chip-select pins are activated
• Data is transmitted from transmit RAM and received into the receive RAM
• The synchronous transfer clock QSPI_CLK is generated
QMR[BAUD] = f
sys/2
MCF5271 Reference Manual, Rev. 2
/ (2 × [desired QSPI_CLK baud rate]
Freescale Semiconductor