MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 536

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Symmetric Key Hardware Accelerator (SKHA)
28.3.4.1 Address Decode Logic
The address decoder translates the internal address to write to the proper SKHA registers.
28.3.4.2 Error Interrupt/Status Logic
This block generates the error interrupt if the host performs an illegal operation. The cause of the
error is flagged in the SKHA error status register
(Section 28.2.1.5, “SKHA Error Status Register
(SKESR)”) and an interrupt is triggered to the interrupt controller. If an error occurs, the SKHA
core engine is halted. This prevents the core from continuing operation with invalid data. These
error interrupts may be masked off selectively by setting the appropriate bits in the SKHA error
status mask register
(Section 28.2.1.6, “SKHA Error Status Mask Register
(SKESMR)”)
28.3.4.3 SKHA Core
The heart of the SKHA is the core processing engine,
Figure
28-17. The core contains the DES
and AES block cipher engines. Also, the cipher mode (ECB, CBC, CTR) is implemented in this
block. The SKHA logic block drives the cipher mode, algorithm, processing direction, key, and
input block to the Mode Control logic.
While DES and AES operate differently internally, the Mode Control logic operates on top of the
AES and DES engines. The Mode Control logic interfaces to both engines and feeds the input
block and key to the selected engine. When the selected engine processes a block, it returns a
"done" signal with the output block. The Mode Control logic in turn returns a "done" signal to the
SKHA logic block along with the processed message block.
When the entire message is processed (following write to the “End of Message” register), the
SKHA logic block sets SKSR[DONE] and generates an interrupt request to the interrupt
controller. This will indicate to the user that it is safe to read context.
MCF5271 Reference Manual, Rev. 2
28-18
Freescale Semiconductor