MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 544

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

IEEE 1149.1 Test Access Port (JTAG)
29.3.1.3 Bypass Register
The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS,
CLAMP, or HIGHZ instructions are selected. After entry into the Capture-DR state, the single-bit
shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the bypass register
is always a logic 0.
29.3.1.4 TEST_CTRL Register
The TEST_CTRL register is a 1-bit shift register path from TDI to TDO when the
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel
hold register on the rising edge of TCLK when the TAP state machine is in the Update-DR state.
The DSE bit selects the drive strength used in JTAG mode.
29.3.1.5 Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST, SAMPLE or
SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on
output pins, and selects a logic value and direction for bidirectional pins or high impedance for
tri-stated pins.
The boundary scan register contains bits for bonded-out and non bonded-out signals excluding
JTAG signals, analog signals, power supplies, compliance enable pins, device configuration pins,
and clock signals.
29-6
31–28
27–22
21–12
11–1
Bits
0
JEDEC
Name
PRN
PIN
DC
ID
Part revision number. Indicate the revision number of the device.
Freescale Design Center number.
Part identification number. Indicate the device number.
Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for
Freescale.
IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and
not the bypass register according to the IEEE standard 1149.1.
Figure 29-3. 1-Bit TEST_CTRL Register
Table 29-4. IDCODE Field Descriptions
MCF5271 Reference Manual, Rev. 2
Reset
W
R
DSE
0
0
Description
Freescale Semiconductor