MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 206

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Control Module (SCM)
11.2.1.5 Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data register to
prevent a CWT time-out. The service sequence requires two writes to this data register: first a write
of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the
CWT time-out, but any number of instructions or accesses to the CWSR can be executed between
11-8
Bits
5–3
7
6
2
1
0
CWTAVAL Core watchdog transfer acknowledge valid.
CWTIF
CWTA
Name
CWRI
CWE
CWT
Core watchdog enable.
0 SWT disabled.
1 SWT enabled.
Core watchdog reset/interrupt select.
0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt
1 Reserved. Please note that unlike legacy devices, this bit is not available since the core
Core watchdog timing delay. These bits select the timeout period for the CWT. At system
reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is
disabled (CWCR[CWE] = 0).
Core watchdog transfer acknowledge enable.
0 CWTA Transfer acknowledge disabled.
1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the
0 CWTA Transfer Acknowledge has not occurred.
1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
Core watchdog timer interrupt flag.
0 CWT interrupt has not occurred
1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.
level for the CWT is programmed in the interrupt control register 7 (ICR7) of INTC0.
watchdog is unable to reset the device.
unacknowledged assertion of the CWT interrupt, the transfer acknowledge asserts,
which allows CWT to terminate a bus cycle and allow the interrupt acknowledge to
occur.
Table 11-5. CWCR Field Description
MCF5271 Reference Manual, Rev. 2
CWT [2:0]
000
001
010
100
101
011
110
111
Description
2
2
2
2
2
2
2
CWT Time-Out Period
2
11
13
15
19
23
27
31
9
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
Bus clock frequency
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