MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 204

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Control Module (SCM)
For details on the processor's view of the local SRAM memories, see
Address Register (RAMBAR).”
11.2.1.3 Core Reset Status Register (CRSR)
The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last
type of reset that occurred. The CRSR is updated by the control logic when the reset is complete.
Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent
reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect.
11-6
Bits
6–0
7
The SCM RAMBAR default value of 0x0000_0000 is invalid. The
RAMBAR located in the processor’s CPU space must be initialized
with the valid bit, RAMBAR[V], set before the CPU (or modules) can
access the on-chip SRAM (see
(RAMBAR)” for more information. The SCM RAMBAR is
implemented as 32 bits, all bits may be written and read. Bit fields
[15:10] and [8:0] are not used in the access decode.
The reset status register (RSR) in the reset controller module (see
Chapter 10, “Reset Controller
reset sources except the core watchdog timer.
Name
EXT
Address
—
Reset
W
Figure 11-3. Core Reset Status Register (CRSR)
R
Note: The reset value of EXT depends on the last reset source. All other
bits are initialized to zero.
External reset.
1 An external device driving RESET caused the last reset. Assertion of reset by an
Reserved, should be cleared.
EXT
external device causes the processor core to initiate reset exception processing. All
registers are forced to their initial state.
7
Table 11-4. CRSR Field Descriptions
MCF5271 Reference Manual, Rev. 2
0
6
0
5
NOTE
NOTE
6.2.1, “SRAM Base Address Register
IPSBAR + 0x010
Module”) provides indication of all
0
4
See Note
Description
0
3
2
0
0
Section 6.2.1, “SRAM Base
1
0
0
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