MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 213

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Only trusted bus masters can modify the access control registers. If a non-trusted bus master
attempts to write any of the SACU control registers, the access is aborted with an error termination
and the registers remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus master.
Accordingly, MPR0 is forced to 1 at reset.
11.4.3.2 Peripheral Access Control Registers (PACR0–PACR8)
Access to several on-chip peripherals is controlled by shared peripheral access control registers.
A single PACR defines the access level for each of the two modules. These modules only support
operand reads and writes. Each PACR follows the format illustrated in
PACRs and the modules that they control, refer to
Freescale Semiconductor
Bits
7–4
3–0
Name
MPRn
Figure 11-9. Peripheral Access Control Register (PACRn)
Address
Address
—
Reset
Reset
W
W
R
R LOCK1
Figure 11-8. Master Privilege Register (MPR)
Reserved. Should be cleared.
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
0
0
0
7
7
Table 11-8. MPR Field Descriptions
MCF5271 Reference Manual, Rev. 2
0
0
0
6
6
ACCESS_CTRL1
0
0
0
5
5
IPSBAR + 0x24 + Offset
IPSBAR + 0x020
0
0
0
4
4
Table
LOCK0
MPR3
Description
0
0
3
3
11-11.
MPR2
2
0
2
0
ACCESS_CTRL0
MPR1
1
0
1
1
System Access Control Unit (SACU)
Figure
MPR0
1
0
0
0
11-10. For a list of
11-15