MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 345

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 19
Fast Ethernet Controller (FEC)
19.1
This chapter provides a feature-set overview, a functional block diagram, and transceiver
connection information for both the 10 and 100 Mbps MII (Media Independent Interface), as well
as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming
model are included.
19.1.1 Overview
The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps
Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports three different standard
MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FEC
supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface, which uses a subset of the
MII pins.
19.1.2 Block Diagram
The block diagram of the FEC is shown below. The FEC is implemented with a combination of
hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE
802.3 standards.
Freescale Semiconductor
Introduction
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to
Purpose I/O
Module”) prior to configuring the FEC.
MCF5271 Reference Manual, Rev. 2
NOTE
Chapter 12, “General
19-1