MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 205

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.2.1.4 Core Watchdog Control Register (CWCR)
The core watchdog timer prevents system lockup if the software becomes trapped in a loop with
no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE].
By default it is disabled. If enabled, the watchdog timer requires the periodic execution of a core
watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out,
resulting in a watchdog timer interrupt. If the timer times out and the core watchdog transfer
acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted. If a core
watchdog timer interrupt acknowledge cycle has not occurred after another timeout, CWT TA is
asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus
cycle. The setting of CWCR[CWTAVAL] indicates that the watchdog timer TA was asserted.
To prevent the core watchdog timer from interrupting, the CWSR must be serviced by performing
the following sequence:
Both writes must occur in order before the time-out, but any number of instructions can be
executed between the two writes. This order allows interrupts and exceptions to occur, if
necessary, between the two writes. Caution should be exercised when changing CWCR values
after the software watchdog timer has been enabled with the setting of CWCR[CWE], because it
is difficult to determine the state of the core watchdog timer while it is running. The countdown
value is constantly compared with the time-out period specified by CWCR[CWT]. The following
steps must be taken to change CWT:
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer
transfer acknowledge. The register can be read at any time, but can be written only if the CWT is
not pending. At system reset, the software watchdog timer is disabled.
Freescale Semiconductor
1. Write 0x55 to CWSR.
2. Write 0xAA to the CWSR.
1. Disable the core watchdog timer by clearing CWCR[CWE].
2. Reset the counter by writing 0x55 and then 0xAA to CWSR.
3. Update CWCR[CWT].
4. Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed
in step 3.
Address
Figure 11-4. Core Watchdog Control Register (CWCR)
Reset
W
R
CWE
0
7
CWRI
MCF5271 Reference Manual, Rev. 2
0
6
0
5
IPSBAR + 0x011
CWT
0
4
0
3
CWTA CWTAV
2
0
AL
0
1
Memory Map/Register Definition
CWTIC
0
0
11-7