MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 314

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

External Interface Module (EIM)
17.5.7.1 Line Transfers
A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on
the aligned address; therefore, the bus interface supports line transfers on multiple address
boundaries.
17.5.7.2 Line Read Bus Cycles
Figure 17-12
a basic read bus cycle with the first data transfer sampled on the rising edge of S4, but the next
pipelined burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined
data burst is single cycle until the last one, which can be held for up to two CLKOUT cycles after
TA is asserted. Note that CSn is asserted throughout the burst transfer. This example shows the
timing for external termination, which differs from the internal termination example in
Figure 17-13
and end (negation of TIP) of the transfer.
Figure 17-13
17-12
A[31:0], TSIZ[1:0]
CSn, BSn, OE
CLKOUT
D[31:0]
Table 17-5
and
only in that the address lines change only at the beginning (assertion of TS and TIP)
R/W
shows timing when internal termination is used.
TIP
TS
TA
Figure 17-12. Line Read Burst (2-1-1-1), External Termination
Figure 17-13
shows allowable patterns for line accesses.
Table 17-5. Allowable Line Access Patterns
S0
show a line access read with zero wait states. The access starts like
A[3:2]
S1
00
01
10
11
MCF5271 Reference Manual, Rev. 2
S2
S3
Read
S4
Read
S5
Longword Accesses
S6
0–4–8–C
4–8–C–0
8–C–0–4
C–0–4–8
Read
S7
S8
S9
Read
S10
Freescale Semiconductor
S11 S12 S13