MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 452

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

UART Modules
24.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UISRs, shown in
contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the internal
interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding UISRn bit has
no effect on the output.
The UISRn and UIMRn registers share the same space in memory. Reading this register provides
the user with interrupt status, while writing controls the mask bits.
24-14
Bits
7–1
0
Figure 24-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
True status is provided in the UISRn regardless of UIMRn settings.
UISRn is cleared when the UART module is reset.
Name
(UIMRn)
Address IPSBAR + 0x0210 (UACR0); IPSBAR + 0x0250 (UACR1); IPSBAR +
IEC
Address
(UISRn)
Figure 24-11. UART Auxiliary Control Register (UACRn)
—
Reset
Reset
W
W
R
R
Figure
Reserved, should be cleared.
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an
COS
COS
IPSBAR + 0x0214 (UISR0); IPSBAR + 0x0254 (UISR1); IPSBAR +
external transition on the UnCTS input (if UIMRn[COS] = 1).
0
0
0
7
7
Table 24-9. UACRn Field Descriptions
24-12, provide status for all potential interrupt sources. UISRn
MCF5271 Reference Manual, Rev. 2
0
0
0
0
0
6
6
0
0
0
0
0
5
5
NOTE
0x0290 (UACR2)
0x0294 (UISR2)
0
0
0
0
0
4
4
Description
0
0
0
0
0
3
3
DB
DB
2
0
0
0
2
RXRDY
RXRDY
FFULL/
FFULL/
0
0
1
0
1
TXRDY
TXRDY
IEC
0
0
0
0
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