MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 440

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

UART Modules
The serial communication channel provides a full-duplex asynchronous/synchronous receiver and
transmitter deriving an operating frequency from the internal bus clock or an external clock using
the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting
appropriate start, stop, and parity bits. It outputs the resulting stream on the channel transmitter
serial data output (UnTXD). See
The receiver converts serial data from the channel receiver serial data input (UnRXD) to parallel
format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled
character onto the bus during read operations. The receiver may be polled, interrupt driven, or use
DMA requests for servicing. See
24.1.2
The MCF5271 contains three independent UART modules with the following features:
24-2
• Each can be clocked by an external clock or by the internal bus clock (eliminating a need
• Full-duplex asynchronous/synchronous receiver/transmitter channel
• Quadruple-buffered receiver
• Double-buffered transmitter
• Independently programmable receiver and transmitter clock sources
• Programmable data format:
• Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or
• Automatic wake-up mode for multidrop applications
• Four maskable interrupt conditions
• All three UARTs have DMA request capability
• Parity, framing, and overrun error detection
for an external UART clock).
— 5–8 data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two stop bits
remote loop-back mode
Features
UARTn can be clocked by the DTnIN pin. However, if the timers are
used, then input capture mode is not available for that timer.
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to
Purpose I/O
Module”) prior to configuring the UART module.
Section 24.4.2.1,
Section 24.4.2.2,
MCF5271 Reference Manual, Rev. 2
NOTE
NOTE
“Transmitter.”
“Receiver.”
Chapter 12, “General
Freescale Semiconductor