MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 172

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Power Management
setting of I2SR[IIF] signifies either the completion of one byte transfer or the reception of a calling
address matching its own specified address when in slave receive mode.
In stop mode, the I
external pins. Upon exiting stop mode, the I
reset.
8.3.2.9
In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an interrupt
to exit the low-power modes.
In stop mode, the QSPI stops immediately and freezes operation, register values, state machines,
and external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode
returns the QSPI to operation from the state prior to the low-power mode entry.
8.3.2.10 DMA Timers (DTIM0–DTIM3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode.
This interrupt can be generated when the DMA Timer is in either input capture mode or reference
compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has
a non-zero value and the DMA enable (DMAEN) bit of the DMA timer extended mode register
(DTXMR) is cleared, an interrupt is issued upon a captured input. In reference compare mode,
where the output reference request interrupt enable (ORRI) bit of DTMR is set and the
DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the
reference value.
DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait
or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the
timer will resume operation unless stop mode was exited by reset.
8.3.2.11 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input
sources and generating the interrupt to the processor will be combinational to allow the ability to
wake up the CPU processor during low-power stop mode when all system clocks are stopped.
An interrupt request will cause the CPU to exit a low-power mode only if that interrupt’s priority
level is at or above the level programmed in the interrupt priority mask field of the CPU’s status
register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask
register as well as at the module from which the interrupt request would originate.
8-8
• Clearing the QSPI enable bit (SPE) disables the QSPI function.
• The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode.
Queued Serial Peripheral Interface (QSPI)
2
C Module stops immediately and freezes operation, register values, and
MCF5271 Reference Manual, Rev. 2
2
C resumes operation unless stop mode was exited by
Freescale Semiconductor