MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 158

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Clock Module
After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies
using the alternate count and compare process. If the counters do not match at any comparison
time, then the LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock
criteria is tightened and the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL
tries to lock. Alternating between tight and relaxed lock criteria prevents the lock detect function
from randomly toggling between locked and non-locked status due to phase sensitivities.
Figure 7-11
In external clock mode, the PLL is disabled and cannot lock.
7.4.6.6
Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is
changed, or if an unexpected loss-of-lock condition occurs, the LOCK and LOCKS flags are
cleared. While the PLL is in the non-locked condition, the system clocks continue to be sourced
from the PLL as the PLL attempts to relock. Consequently, during the relocking process, the
system clocks frequency is not well defined and may exceed the maximum system frequency,
violating the system clock timing specifications.
However, once the PLL has relocked, the LOCK flag is set. The LOCKS flag remains cleared if
the loss-of-lock is unexpected. The LOCKS flag is set when the loss-of-lock is caused by changing
7-24
PLL Loss-of-Lock Conditions
shows the sequence for detecting locked and non-locked conditions.
with Tight Lock
Criteria
Start
Number of Feedback
Reference Cycles
Cycles Elapsed
and Compare
Figure 7-11. Lock Detect Sequence
Count N
MCF5271 Reference Manual, Rev. 2
≠
Reference Count
Feedback Count
In Same Count/Compare Sequence
Feedback Count = N
Condition and Notify
Reference Count =
Set Relaxed Lock
and Notify System of Loss
System of Lock
Lock Detected.
Loss-of-Lock Detected
Set Tight Lock Criteria
Condition
of Lock Condition
Reference Count =
Feedback Count = N + K
IN Same Count/Compare Sequence
Reference Count
≠
Feedback Count
and Compare Number
of Feedback Cycles
Reference Cycles
Count N + K
Elapsed
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