MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 180

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Configuration Module (CCM)
9.3.3
The following subsection describes the CCM registers.
9.3.3.1
9-4
Address
1
2
3
4
Reset
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in
a cycle termination transfer error.
See
writes to this register.
Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
14–7
Bits
W
15
R LOAD
6
Chapter 8, “Power Management,”
Note: The reset value of the LOAD field is determined during reset configuration. The SZEN is set and the BME
bit is set to enable the bus monitor and all other bits in the register are cleared at reset.
Register Descriptions
15
Chip Configuration Register (CCR)
To safeguard against unintentionally activating test logic, write
0x0000 to the above reserved location during initialization
(immediately after reset) to lock out test features. Setting any bits in
the CCR may lead to unpredictable results.
Name
LOAD
SZEN
14
0
—
13
0
Figure 9-2. Chip Configuration Register (CCR)
Pad driver load. The LOAD bit selects full or partial drive strength for selected pad output
0 Default drive strength.
1 Full drive strength.
Table 9-2
Reserved, should be cleared.
TSIZ[1:0] enable. This read/write bit enables the TSIZ[1:0] function of the external pins.
0 TSIZ[1:0] function disabled. DMA Acknowlede function enabled on the TSIZ[1:0] pins.
1 TSIZ[1:0] function enabled. DMA Acknowlede function disabled on the TSIZ[1:0] pins.
drivers. For maximum capacitive load, set the LOAD bit to select full drive strength. For
reduced power consumption and reduced electromagnetic interference (EMI), clear the
LOAD bit to select partial drive strength.
12
0
Table 9-4. CCR Field Descriptions
11
shows the read/write accessibility of this write-once bit.
0
MCF5271 Reference Manual, Rev. 2
for a description of the LPCR. It is shown here only to warn against accidental
10
0
9
0
IPSBAR + 0x11_0004
NOTE
0
8
See Note
0
7
Description
SZEN PSTEN
6
5
0
4
BME
3
Freescale Semiconductor
2
BMT
1
0