MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 389

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.3.10 Full Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received pause
frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause
duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN]
asserted) and flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame
when the fields of the incoming frame match the pause frame specifications, as shown in the table
below. In addition, the receive status associated with the frame should indicate that the frame is
valid.
Pause frame detection is performed by the receiver and microcontroller modules. The
microcontroller runs an address recognition subroutine to detect the specified pause frame
destination address, while the receiver detects the type and opcode pause frame fields. On
detection of a pause frame, TCR[GTS] is set by the FEC internally. When transmission has paused,
the EIR[GRA] interrupt is asserted and the pause timer begins to increment. Note that the pause
timer makes use of the transmit backoff timer hardware, which is used for tracking the appropriate
collision backoff time in half-duplex mode. The pause timer increments once every slot time, until
OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is
deasserted allowing MAC data frame transmission to resume. Note that the receive flow control
pause (TCR[RFC_PAUSE]) status bit is set while the transmitter is paused due to reception of a
pause frame.
Freescale Semiconductor
Table 19-36. Destination Address to 6-Bit Hash (Continued)
48-bit Destination Address
16-bit PAUSE Duration
48-bit Source Address
Table 19-37. PAUSE Frame Field Specification
16-bit Opcode
16-bit Type
5d:ff:ff:ff:ff:ff
7d:ff:ff:ff:ff:ff
dd:ff:ff:ff:ff:ff
9d:ff:ff:ff:ff:ff
bd:ff:ff:ff:ff:ff
fd:ff:ff:ff:ff:ff
48-bit DA
MCF5271 Reference Manual, Rev. 2
6-bit Hash (in
0x0180_c200_0001 or Physical Address
0x3a
0x3b
0x3d
0x3e
hex)
0x3c
0x3f
0x0000–0xFFFF
0x8808
0x0001
Hash Decimal
Any
Value
58
59
60
61
62
63
Functional Description
19-45