MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 263

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

controller also loads the level and priority number for the level into the IACKLPR register, where
it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK
is a useful concept that allows an interrupt service routine to determine if there are other pending
interrupts so that the overhead associated with interrupt exception processing (including machine
state save/restore functions) can be minimized. In general, the software IACK is performed near
the end of an interrupt service routine, and if there are additional active interrupt sources, the
current interrupt service routine (ISR) passes control to the appropriate service routine, but without
taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number
associated with the highest level, highest priority unmasked interrupt source for that interrupt
controller. The IACKLPR register is also loaded as the software IACK is performed. If there are
no active sources, the interrupt controller returns an all-zero vector as the operand. For this
situation, the IACKLPR register is also cleared.
In addition to the software IACK registers within each interrupt controller, there are global
software IACK registers. A read from the global SWIACK will return the vector number for the
highest level and priority unmasked interrupt source from all interrupt controllers. A read from one
of the LnIACK registers will return the vector for the highest priority unmasked interrupt within
a level for all interrupt controllers.
13.3
The System Control Module (SCM) contains an 8-bit low-power interrupt control register
(LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be
programmed by software to enter low-power mode.
Freescale Semiconductor
Figure 13-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
Bits
7–0
Low-Power Wakeup Operation
Table 13-14. SWIACK and L1IACK-L7IACK Field Descriptions
VECTOR
Name
Address
Reset
W
R
Vector number. A read from the SWIACK register returns the vector number associated
with the highest level, highest priority unmasked interrupt source. A read from one of the
LnACK registers returns the highest priority unmasked interrupt source within the level.
0
7
See
MCF5271 Reference Manual, Rev. 2
0
6
Table 13-2
0
5
and
0
4
VECTOR
Table 13-3
Description
0
3
for register offsets
2
0
0
1
Low-Power Wakeup Operation
0
0
13-15