MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 554

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
30.3.1 Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be
displayed on DDATA depending on the CSR settings. CSR also controls the number of address
bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA
nibble that begins the data output.
Bytes are displayed in least-to-most-significant order. The processor captures only those target
addresses associated with taken branches which use a variant addressing mode, that is, RTE and
RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing
modes, and all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code for a C
language case statement. Typically, the evaluation of this statement uses the variable of an
expression as an index into a table of offsets, where each offset points to a unique case within the
structure. For such change-of-flow operations, the MCF5271 uses the debug pins to output the
following sequence of information on successive processor clock cycles:
30-4
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the
0x8–
Hex
0xC
0xD
0xB
0xE
0xF
PST[3:0]
DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.
Binary
1000–
1011
1100
1101
1110
1111
Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock
cycles. The value is driven onto the PST port one PSTCLK cycle before the data is displayed on
DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception
processing completes.
Processor is stopped. Appears in multiple-cycle format when the MCF5271 executes a STOP
instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs
display 0xE until the stopped mode is exited
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display
0xF until the processor is restarted or reset. (see
Table 30-2. Processor Status Encoding (Continued)
MCF5271 Reference Manual, Rev. 2
.
Definition
Section 30.5.1, “CPU
Halt”)
Freescale Semiconductor