MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 403

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.2.1 Register Description
The PIT programming model consists of these registers:
21.2.1.1 PIT Control and Status Register (PCSRn)
Freescale Semiconductor
• The PIT control and status register (PCSRn) configures the timer’s operation.
• The PIT modulus register (PMRn) determines the timer modulus reload value.
• The PIT count register (PCNTRn) provides visibility to the counter value.
Address
Reset
1
2
Table 21-2. Programmable Interrupt Timer Modules Memory Map (Continued)
IPSBAR Offset
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
Accesses to reserved address locations have no effect and result in a cycle termination transfer error.
W
0x15_0008–
0x16_0008–
0x17_0008–
0x18_0008–
R
0x15_FFFF
0x16_FFFF
0x17_FFFF
0x18_FFFF
0x16_0000
0x16_0004
0x17_0000
0x17_0004
0x18_0000
0x18_0004
15
0
0
14
0
0
Figure 21-2. PIT Control and Status Register (PCSRn)
13
0
0
PIT Control and Status Register
PIT Control and Status Register
PIT Control and Status Register
PIT Count Register (PCNTR1)
PIT Count Register (PCNTR2)
PIT Count Register (PCNTR3)
[31:24]
IPSBAR + 0x0015_0000 (PIT0); IPSBAR + 0x0016_0000 (PIT1);
IPSBAR + 0x0017_0000 (PIT2); IPSBAR + 0x0018_0000 (PIT3)
12
0
0
(PCSR1)
(PCSR2)
(PCSR3)
11
0
MCF5271 Reference Manual, Rev. 2
10
0
PRE
[23:16]
0
9
Reserved
Reserved
Reserved
Reserved
0
8
PIT Modulus Register (PMR1)
PIT Modulus Register (PMR2)
PIT Modulus Register (PMR3)
0
0
7
[15:8]
DOZE DBG OVW PIE
6
0
Reserved
Reserved
Reserved
0
5
2
2
2
0
4
[7:0]
Memory Map/Register Definition
0
3
PIF
0
2
Access
S/U
S/U
S/U
RLD
—
—
—
—
S
S
S
0
1
1
EN
0
0
21-3