MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 181

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

9.3.3.2
At reset, RCON determines the default operation of certain chip functions. All default functions
defined by the RCON values can only be overridden during reset configuration (see
“Reset
Freescale Semiconductor
Address
Reset
W
Bits
R
2–0
Configuration”) if the external RCON pin is asserted. RCON is a read-only register.
5
4
3
15
0
0
Reset Configuration Register (RCON)
PSTEN
14
0
0
Name
BME
BMT
—
13
0
0
Figure 9-3. Reset Configuration Register (RCON)
Table 9-4. CCR Field Descriptions (Continued)
PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and
Debug Data (DDATA)n functions of the external pins.
0 PST/DDATA function disabled.
1 PST/DDATA function enabled.
Reserved, should be cleared.
Bus monitor enable. This read/write bit enables the bus monitor to operate during external
bus cycles.
0 Bus monitor disabled for external bus cycles.
1 Bus monitor enabled for external bus cycles.
Table 9-2
Bus monitor timing. This field selects the timeout period (in system clocks) for the bus
monitor.
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
Table 9-2
12
0
0
11
0
0
shows the read/write accessibility of this write-once bit.
shows the read/write accessibility of this write-once bit.
MCF5271 Reference Manual, Rev. 2
10
0
0
9
0
RCSC
IPSBAR + 0x11_0008
0
8
7
0
0
Description
0
0
6
RLOAD
0
5
BOOTPS
0
4
Memory Map/Register Definition
3
0
0
0
2
Section 9.4.1,
0
0
1
MODE
0
1
9-5