MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 622

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Reset controller
RNG
S
SACU 11-12
SCM
SDRAM controller
Index-8
control flow 10-6
low-power modes 8-9
memory map 10-2
registers
requests
reset sources 10-4
signals
status flags 10-9
memory map 27-1
registers
low-power modes 8-6
memory map 11-2
registers
SACU 11-12
auto-refresh 18-16
burst page mode 18-14
example
mode 1 (UMR1n) 24-5
mode 2 (UMRn) 24-7
output port command (UOP1n/UOP0n) 24-16
receive buffers (URBn) 24-12
status (USRn) 24-8
transmit buffers (UTBn) 24-12
control (RCR) 10-2
status (RSR) 10-3
internal 10-8
synchronous 10-8
RESET 10-2
RSTOUT 10-2
control (RNGCR) 27-1
entropy (RNGER) 27-3
output FIFO (RNGOUT) 27-4
status (RNGSR) 27-2
bus master park (MPARK) 11-11
core reset status (CRSR) 11-6
core watchdog control (CWCR) 11-7
core watchdog service (CWSR) 11-8
grouped peripheral access control (GPACR) 11-17
IPSBAR 11-3
master privilege (MPR) 11-14
peripheral access control (PACRn) 11-15
RAMBAR 3-8
DACR initialization 18-21
DCR initialization 18-21
DMR initialization 18-23
initialization code 18-25
interface configuration 18-20
,
–
11-4
10-6
MCF5271 Reference Manual, Rev. 2
Signals
initialization 18-18
interfacing 18-14
memory map 18-5
operation 18-9
registers
self-refresh 18-17
signals
block diagram 2-2
bus 17-1
CCM
chip select module
clock module
debug
external boot mode 2-15
JTAG
QSPI
low-power modes 8-6
synchronous
address and control 0–1 (DACRn) 18-6
control (DCR) 18-5
mask (DMRn) 18-9
mode register
summary 18-4
CLKMOD1–0 9-2
RCON 9-2
byte strobes (BS3–0) 16-2
chip select (CS7–0) 16-1
output enable (OE) 16-1
CLKMOD1–0 7-7
CLKOUT 7-7
EXTAL 7-7
RSTOUT 7-7
XTAL 7-7
breakpoint (BKPT) 30-2
debug data (DDATA3–0) 30-2
development serial clock (DSCLK) 30-2
development serial input (DSI) 30-2
development serial output (DSO) 30-2
processor status (PST3–0) 30-2
PSTCLK 30-2
JTAG_EN 29-3
TCLK 29-4
test data input/development serial input
test data output/development serial output
test mode select/breakpoint (TMS/BKPT) 29-4
test reset/development serial clock
summary 23-2
address multiplexing 18-9
initialization 18-24
settings 18-19
(TDI/DSI) 29-4
(TDO/DSO) 29-5
(TRST/DSCLK) 29-4
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