MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 551

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 30
Debug Support
30.1
This chapter describes the Revision A enhanced hardware debug support in the MCF5271.
30.1.1 Overview
The debug module is shown in
Debug support is divided into three areas:
Freescale Semiconductor
• Real-time trace support—The ability to determine the dynamic execution path through an
• Background debug mode (BDM)—Provides low-level debugging in the ColdFire
• Real-time debug support—BDM requires the processor to be halted, which many real-time
application is fundamental for debugging. The ColdFire solution implements an 8-bit
parallel output bus that reports processor execution status and data to an external emulator
system. See
processor complex. In BDM, the processor complex is halted and a variety of commands
can be sent to the processor to access memory and registers. The external emulator uses a
three-pin, serial, full-duplex channel. See
(BDM),” and
embedded applications cannot do. Debug interrupts let real-time systems execute a unique
service routine that can quickly save the contents of key registers and variables and return
the system to normal operation. External development systems can access saved data
because the hardware supports concurrent operation of the processor and BDM-initiated
commands. See
Introduction
Section 30.3, “Real-Time Trace
Section 30.4, “Memory Map/Register
Control
BKPT
Figure 30-1. Processor/Debug Module Interface
Section 30.6, “Real-Time Debug
PST[3:0], DDATA[3:0]
ColdFire CPU Core
Figure
Debug Module
Trace Port
PSTCLK
MCF5271 Reference Manual, Rev. 2
30-1.
Communication Port
DSCLK, DSI, DSO
Section 30.5, “Background Debug Mode
Support.”
Support.”
Definition.”
High-speed
core bus
(f
sys
)
30-1