MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 160

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Clock Module
7.4.6.11 Loss-of-Clock Interrupt Request
When a loss-of-clock condition is detected, the PLL will request an interrupt if the LOCIRQ bit in
the SYNCR is set. The LOCIRQ bit has no affect in external clock mode or if LOCEN is cleared.
7.4.6.12 Alternate Clock Selection
Depending on which clock source fails, the loss-of-clock circuit switches the system clocks source
to the remaining operational clock. The alternate clock source generates the system clocks until
reset is asserted. As
self-clocked mode (SCM). The PLL remains in SCM until the next reset. When the PLL is
operating in SCM, the system frequency depends on the value in the RFD field. The SCM system
frequency stated in electrical specifications assumes that the RFD has been programmed to binary
000. If the loss-of-clock condition is due to PLL failure, the PLL reference becomes the system
clocks source until the next reset, even if the PLL regains and relocks.
A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures
may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes
priority and the PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the
next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both
the reference and the PLL must be functioning properly to exit reset.
7.4.6.13 Loss-of-Clock in Stop Mode
Table 7-11
clocked by the various clocking methods.
7-26
EXT
MODE
In
1
The LOC circuit monitors the reference and feedback inputs to the PFD. See
External
X
Clock
Mode
PLL
X
shows the resulting actions for a loss-of-clock in Stop Mode when the device is being
X
System Clock Source
X
Before Failure
External clock
X
Table 7-10
Table 7-11. Stop Mode Operation (Sheet 1 of 5)
PLL
X
Table 7-10. Loss-of-Clock Summary
Expected
Action at
Stop
PLL
—
shows, if the reference fails, the PLL goes out of lock and into
MCF5271 Reference Manual, Rev. 2
Reference Failure Alternate
Clock Selected by LOC
Lose reference
clock
PLL self-clocked mode
Circuit
During Stop
PLL Action
—
1
None
Until Reset
EXT
Stuck
MODE
Out
0
Figure
—
Clock Selected by LOC
PLL Failure Alternate
Circuit Until Reset
7-10.
PLL reference
0
—
NA
0
Freescale Semiconductor
—
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