MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 70

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
3.2.1.5
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. Bit 4, the extend bit (X bit), is also used as an input operand
during multiprecision arithmetic computations.
3.2.2
The registers in the EMAC portion of the user programming model, are described in
“Enhanced Multiply-Accumulate Unit
3-4
• Four 48-bit accumulator registers partitioned as follows:
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values
• One 16-bit mask register (MASK)
— Four 32-bit accumulators (ACC0–ACC3)
— Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into
Accumulators and extension bytes can be loaded, copied, and stored, and results from
EMAC arithmetic operations generally affect the entire 48-bit destination.
for load and store operations (ACCext01 and ACCext23)
EMAC Register Description
two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Bits
7–5
Condition Code Register (CCR)
4
3
2
1
0
Address
Reset
Field
Name
—
N
C
X
Z
V
Figure 3-3. Condition Code Register (CCR)
0
0
7
Reserved, should be cleared
Extend condition code bit. Set to the value of the C-bit for arithmetic operations;
otherwise not affected or set to a specified result.
Negative condition code bit. Set if the most significant bit of the result is set;
otherwise cleared.
Zero condition code bit. Set if the result equals zero; otherwise cleared.
Overflow condition code bit. Set if an arithmetic overflow occurs implying that the
result cannot be represented in the operand size; otherwise cleared.
Carry condition code bit. Set if a carry out of the operand msb occurs for an
addition, or if a borrow occurs in a subtraction; otherwise cleared
Set to the value of the C bit for arithmetic operations; otherwise not affected.
Table 3-1. CCR Field Descriptions
MCF5271 Reference Manual, Rev. 2
0
0
6
(EMAC),” and include the following registers:
0
0
5
LSB of Status Register (SR)
X
0
4
N
0
3
Description
Z
2
0
V
0
1
C
0
0
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