MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 131

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
11–10
Bits
7–6
5–1
9
8
0
C/I, SC, SD,
UC, UD
Name
PRI1
PRI0
SPV
WP
—
V
Table 6-1. RAMBAR Field Descriptions (Continued)
Priority bit. PRI1 determines if DMA/FEC or CPU has priority in upper 32k bank of memory.
PRI0 determines if DMA/FEC or CPU has priority in lower 32k bank of memory. If bit is set,
DMA/FEC has priority. If bit is cleared, CPU has priority. Priority is determined according
to the following table.
Note: The recommended setting for the priority bits is 00.
Secondary port valid. Allows access by DMA and FEC
0 DMA and FEC access to memory is disabled.
1 DMA and FEC access to memory is enabled.
Note: The BDE bit in the second RAMBAR register must also be set to allow dual port
access to the SRAM. For more information, see
Register (RAMBAR).”
Write protect. Allows only read accesses to the SRAM. When this bit is set, any attempted
write access will generate an access error exception to the ColdFire processor core.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module
Reserved, should be cleared.
Address space masks (ASn)
These five bit fields allow certain types of accesses to be “masked,” or inhibited from
accessing the SRAM module. The address space mask bits are:
C/I = CPU space/interrupt acknowledge cycle mask
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address
These bits are useful for power management as detailed in
Management.”
Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module;
otherwise, the module is disabled.
0 Contents of RAMBAR are not valid
1 Contents of RAMBAR are valid
space is made, it is inhibited from accessing the SRAM module, and is processed like
any other non-SRAM reference.
MCF5271 Reference Manual, Rev. 2
PRI[1:0]
00
01
10
11
Upper Bank Priority
DMA/FEC Accesses
DMA/FEC Accesses
CPU Accesses
CPU Accesses
Description
Section 11.2.1.2, “Memory Base Address
Lower Bank Priority
DMA/FEC Accesses
DMA/FEC Accesses
CPU Accesses
CPU Accesses
Section 6.2.4, “Power
Register Description
6-3