MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 119

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.1.3
The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches
from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the
debug module's memory references appear as supervisor data accesses but the unit can be
programmed to generate user-mode accesses and/or instruction fetches. The cache processes any
fetch access in the normal manner.
5.1.3.1
Because both the cache and high-speed SRAM module are connected to the ColdFire core's local
data bus, certain user-defined configurations can result in simultaneous fetch processing.
If the referenced address is mapped into the SRAM module, that module will service the request
in a single cycle. In this case, data accessed from the cache is simply discarded and no external
memory references are generated. If the address is not mapped into the SRAM space, the cache
handles the request in the normal fashion.
Freescale Semiconductor
31
Operation
Interaction with Other Modules
Local Address Bus
12
4 3
1 2
0
Figure 5-1. Cache Block Diagram
Fill Hit
=
MCF5271 Reference Manual, Rev. 2
I or D Line
31
31
Tag Hit
TAG
=
Buffer
Address
13
4
511
0
I or D Line Buffer Storage
External Data[31:0]
Local Data Bus
31
MUX
DATA
MUX
0
2047
0
Introduction
5-3