MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 260

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Interrupt Controller Modules
13.2.1.6 Interrupt Control Register (ICRx, (x = 1, 2,..., 63))
Each ICRx specifies the interrupt level (1–7) and the priority within the level (0–7). All ICRx
registers can be read, but only ICR8 to ICR63 can be written. It is the responsibility of the software
to program the ICRx registers with unique and non-overlapping level and priority definitions.
Failure to program the ICRx registers in this manner can result in undefined behavior. If a specific
interrupt request is completely unused, the ICRx value can remain in its reset (and disabled) state.
13-12
Bits
Bits
6–4
3–0
7–6
5–3
2–0
LEVEL
Name
Name
PRI
Address
—
IL
IP
Table 13-11. IACKLPR Field Descriptions (Continued)
Reset
R:
W
Figure 13-9. Interrupt Control Register (ICRx)
Note: Read only for ICR1-ICR7, else Read/Write
Note: It is the responsibility of the software to program the ICRnx
registers with unique and non-overlapping level and priority definitions.
Failure to program the ICRnx registers in this manner can result in
undefined behavior. If a specific interrupt request is completely unused,
the ICRnx value can remain in its reset (and disabled) state.
Interrupt level. Represents the interrupt level currently being acknowledged.
Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently
being acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only
Reserved, should be cleared.
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
Interrupt priority. Indicates the interrupt priority for internal modules within the
interrupt-level assignment. 000 represents the lowest priority and 111 represents the
highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the
level, and the IP field will always read as 000.
0
0
7
Table 13-12. ICRx Field Descriptions
See
MCF5271 Reference Manual, Rev. 2
0
0
6
Table 13-2
0
5
and
IL
0
4
Table 13-3
Description
Description
0
3
See Note
for register offsets
2
0
IP
0
1
0
0
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