MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 214

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Control Module (SCM)
11-16
Bits
6–4
2–0
7
3
ACCESS_
ACCESS_
LOCK1
LOCK0
CTRL1
CTRL0
Name
Table 11-11. Peripheral Access Control Registers (PACRn)
IPSBAR Offset
0x02A
0x02B
0x02C
0x024
0x025
0x026
0x027
0x028
0x029
Table 11-10. PACR ACCESS_CTRL Bit Encodings
This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to
the PACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in
This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to
the PACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in
Bits
000
001
010
100
101
011
110
111
Table 11-9. PACRn Field Descriptions
MCF5271 Reference Manual, Rev. 2
PACR0
PACR1
PACR2
PACR3
PACR4
PACR5
PACR6
PACR7
Name
—
Read
Supervisor Mode
—
x
x
x
x
x
x
x
Write
ACCESS_CTRL1
—
—
—
—
x
x
x
x
UART0
UART2
DTIM0
DTIM2
INTC0
SCM
EIM
I
Description
—
2
C
Modules Controlled
Table
Table
Read
—
—
—
—
x
x
x
x
11-10.
11-10.
User Mode
ACCESS_CTRL0
SDRAMC
Write
UART1
DTIM1
DTIM3
INTC1
—
—
—
—
—
—
QSPI
x
x
DMA
—
—
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