MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 307

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 17-3
Basic operation of the MCF5271 bus is a three-clock bus cycle.
17.5.2 Data Transfer Cycle States
The data transfer operation in the MCF5271 is controlled by an on-chip state machine. Each bus
clock cycle is divided into two states. Even states occur when CLKOUT is high and odd states
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• Should an address and attribute match in multiple CSCRs, the matching chip-select signals
• Should an address and attribute match both DACRs or a DACR and a CSCR, the operation
1. During the first clock, the address, attributes, and TS are driven.
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the
3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide
are driven; however, the MCF5271 runs an external burst-inhibited bus cycle with external
termination on a 32-bit port.
is undefined.
external device provides data and is sampled at the rising edge at the end of the second bus
clock. This data is concurrent with TA, which is also sampled at the rising edge of the
clock.
During a write, the ColdFire device drives data from the rising clock edge at the end of the
first clock to the rising clock edge at the end of the bus cycle. Wait states can be added
between the first and second clocks by delaying the assertion of TA. TA can be configured
to be generated internally through the CSCRs. If TA is not generated internally, the system
must provide it externally.
hold time for address, attributes and write data.
basic read and write operations.
Number of CSCR Matches
shows the type of access as a function of match in the CSCRs and DACRs.
Table 17-3. Accesses by Matches in CSCRs and DACRs
Multiple
Multiple
Multiple
0
1
0
1
0
1
MCF5271 Reference Manual, Rev. 2
Number of DACR Matches
Multiple
Multiple
Multiple
0
0
0
1
1
1
Figure 17-6
External
Defined by CSCR
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
Type of Access
and
Figure 17-8
Data Transfer Operation
show the
17-5