MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 421

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 23
Queued Serial Peripheral Interface (QSPI)
Module
23.1 Introduction
This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature
set overview is a description of operation including details of the QSPI’s internal RAM
organization. The chapter concludes with the programming model and a timing diagram.
23.1.1 Overview
The queued serial peripheral interface module provides a serial peripheral interface with queued
transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU
intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address
and data registers.
23.1.2 Features
23.1.3 Module Description
The QSPI module communicates with the integrated ColdFire CPU using internal memory
mapped registers starting at IPSBAR + 0x340. See
Definition.” A block diagram of the QSPI module is shown in
Freescale Semiconductor
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines for control of up to 15 devices
• Baud rates from 147.1 Kbps to 18.75 Mbps at 75 MHz
• Programmable delays before and after transfers
• Programmable QSPI clock phase and polarity
• Supports wraparound mode for continuous transfers
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to
Purpose I/O
Module”) prior to configuring the QSPI Module.
MCF5271 Reference Manual, Rev. 2
NOTE
Section 23.3, “Memory Map/Register
Chapter 12, “General
Figure
23-1.
23-1