MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 334

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
Accesses in synchronous burst page mode always cause the following sequence:
18.3.4.4 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is responsible for
providing timing and control to refresh the SDRAM without user interaction. Once the refresh
counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh
18-16
SDRAM_CS[0] or [1]
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
ACTV
NOP
NOP
port size.
PALL
DQM[3:0]
SYSCLK
DRAMW
commands to assure SD_SRAS-to-SD_SCAS delay (if CAS latency is 1, there are no
commands).
D[31:0]
A[31:0]
command
command
SRAS
SCAS
OE
t
CASL
ACTV
Row
Figure 18-7. Burst Write SDRAM Access
= 2
READ
NOP
NOP
or
MCF5271 Reference Manual, Rev. 2
Column
WRITE
WRITE
commands to assure the
commands to service the transfer size with the given
Column Column
WRITE
WRITE
t
RWL
WRITE
ACTV
Column
-to-precharge delay.
NOP
ACTV
PALL
delay.
Freescale Semiconductor
t
RP