MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 369

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.2.4.19 FIFO Receive Bound Register (FRBR)
The FRBR is an 8-bit register that the user can read to determine the upper address bound of the
FIFO RAM. Drivers can use this value, along with the FRSR to appropriately divide the available
FIFO RAM between the transmit and receive data paths.
Freescale Semiconductor
Address
Address
Reset
Reset
Reset
Reset
31–2
Bits
1–0
W
W
W
W
R
R
R
R
31
15
31
15
0
0
0
0
0
0
0
0
Figure 19-19. FIFO Transmit FIFO Watermark Register (TFWR)
TFWR
Name
30
14
30
14
0
0
0
0
0
0
0
0
—
Figure 19-20. FIFO Receive Bound Register (FRBR)
29
13
29
13
0
0
0
0
0
0
0
0
Reserved, should be cleared.
Number of bytes written to transmit FIFO before transmission of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
28
12
Table 19-22. TFWR Field Descriptions
28
12
0
0
0
0
0
0
0
0
27
27
11
11
0
0
0
0
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
26
10
0
0
0
0
0
0
0
1
25
25
0
0
0
0
0
0
1
9
9
IPSBAR + 0x114C
IPSBAR + 0x1144
24
24
0
0
0
0
0
0
0
8
8
Descriptions
23
23
0
0
0
0
0
0
0
7
7
R_BOUND
22
22
0
0
6
0
0
0
0
6
0
21
21
0
0
0
0
0
0
0
5
5
20
20
0
0
0
0
0
0
0
4
4
Memory Map/Register Definition
19
19
0
0
0
0
0
0
0
3
3
18
18
0
0
0
0
0
0
0
2
2
17
17
0
0
0
0
0
0
0
1
1
TFWR
16
16
0
0
0
0
0
0
0
0
0
19-25