MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 443

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.3.1
The UMR1n registers control configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a
UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
Freescale Semiconductor
1
2
0x00_021C
0x00_025C
0x00_029C
0x00_023C
0x00_027C
0x00_02BC
0x00_02B4
0x00_02B8
0x00_0210
0x00_0250
0x00_0290
0x00_0214
0x00_0254
0x00_0294
0x00_0218
0x00_0258
0x00_0298
0x00_0234
0x00_0274
0x00_0238
0x00_0278
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset
command. That is, if channel operation is not disabled, undesirable results may occur.
This address is for factory testing. Reading this location results in undesired effects and possible incorrect
transmission or reception of characters. Register contents may also be changed.
IPSBAR
UART0
UART1
UART2
Offset
UART Mode Registers 1 (UMR1n)
(Read) UART Input Port Change Register
(UIPCRn)
(Write) UART Auxiliary Control Register
(Read) UART interrupt Status Register (UISRn)
(Write) UART Interrupt Mask Register (UIMRn)
(Read) Do not access
(Write) UART Divider Upper Register (UBG1n)
(Read) Do not access
(Write) UART Divider Lower Register (UBG2n)
(Read) UART Input Port Register (UIPn)
(Write) Do not access
(Read) Do not access
(Write) UART Output Port Bit Set Command
Register (UOP1n)
(Read) Do not access
(Write) UART Output Port Bit Reset Command
Register (UOP0n)
Table 24-2. UART Module Memory Map (Continued)
[31:24]
2
2
2
2
2
MCF5271 Reference Manual, Rev. 2
1
(UACRn)
RESET MODE REGISTER POINTER
[23:16]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[15:8]
Memory Map/Register Definition
command using
[7:0]
24-5