MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 212

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Control Module (SCM)
11.4.3 Memory Map/Register Definition
The memory map for the SACU program-visible registers within the System Control Module
(SCM) is shown in
11.4.3.1 Master Privilege Register (MPR)
The MPR specifies the access privilege level associated with each bus master in the platform. The
register provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet
Controller), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (), and bit 0 to master 0 (ColdFire
core).
11-14
IPSBA
• Peripheral access control registers (PACRs)
• Grouped peripheral access control registers (GPACR0)
0x03C
0x020
0x024
0x028
0x030
0x034
0x038
Offset
0x02c
R
— The reset state provides supervisor privilege to the processor core (bus master 0).
— Input signals allow the non-core bus masters to have their user/supervisor attribute
— Nine 8-bit registers control access to 17 of the on-chip peripheral modules.
— Provides read/write access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to these modules
— One single register (GPACR) controls access to 14 of the on-chip peripheral modules
— Provide read/write/execute access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to each of these peripheral spaces
– Enable the master’s user/supervisor attribute
enabled at reset. This is intended to support the concept of a trusted bus master, and also
controls the ability of a bus master to modify the register state of any of the SACU
control registers; that is., only trusted masters can modify the control registers.
[31:28]
GPACR
PACR0
PACR4
PACR7
MPR
Figure
—
—
—
[27:24]
11-7. The MPR, PACR, and GPACR are 8 bits in width.
Table 11-7. SACU Register Memory Map
MCF5271 Reference Manual, Rev. 2
[23:20]
—
PACR1
—
—
—
—
—
—
[19:16]
—
[15:12]
—
PACR2
PACR5
PACR8
—
—
—
—
[11:8]
—
Freescale Semiconductor
[7:4]
—
PACR6
PACR3
—
—
—
—
—
[3:0]
—