MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 485

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

25.5.4 I
This I2SR contains bits that indicate transaction direction and status.
Freescale Semiconductor
Bits
Bits
1–0
2
7
6
5
4
3
2
C Status Register (I2SR)
Name
Name
RSTA
IAAS
Address
ICF
IBB
IAL
—
—
Reset
W
Table 25-4. I2CR Field Descriptions (Continued)
R
Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes
loss of arbitration.
0 No repeat start
1 Generates a repeated START condition.
Reserved, should be cleared.
Data transferring bit. While one byte of data is transferred, ICF is cleared.
0 Transfer in progress
1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
I
must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
I
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by
software by writing zero to it.)
Reserved, should be cleared.
2
2
• I2C_SDA sampled low when the master drives high during an address or data-transmit
• I2C_SDA sampled low when the master drives high during the acknowledge bit of a
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU
C bus busy bit. Indicates the status of the bus.
ICF
cycle.
data-receive cycle.
Figure 25-12. I
1
7
Table 25-5. I2SR Field Descriptions
IAAS
MCF5271 Reference Manual, Rev. 2
0
6
IBB
0
5
2
IPSBAR + 0x00_030C
C Status Register (I2SR)
IAL
0
4
Description
Description
0
0
3
SRW
2
0
IIF
0
1
Memory Map/Register Definition
RXAK
1
0
25-11