MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 585

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Command/Result Formats:
Command Sequence:
Operand Data:
Result Data:
30.5.3.3.11 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register
selection for the
CSR[FOF, TRG, HALT, BKPT]; as well as the trigger status bits (CSR[BSTAT]) if either a level-2
breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint
has been enabled.
Command/Result Formats:
Freescale Semiconductor
Command
WCREG
???
Result
15
RDMREG
’NOT READY’
MS ADDR
14
This instruction requires two longword operands. The first selects the
register to which the operand data is to be written; the second contains the
data.
Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern
of 0x0001.
0x2
0x0
0x0
Figure 30-35.
13
Figure 30-36.
command is CSR (DRc = 0x00). Note that this read of the CSR clears
12
’NOT READY’
MCF5271 Reference Manual, Rev. 2
MS ADDR
11
WCREG
10
WCREG
0x8
0x0
Command/Result Formats
9
Command Sequence
’NOT READY’
RDMREG
D[31:16]
8
D[15:0]
MS DATA
’NOT READY’
LS DATA
7
)
6
0x8
0x0
R
c
5
REGISTER
CONTROL
WRITE
4
Background Debug Mode (BDM)
3
’CMD COMPLETE’
’NOT READY’
2
NEXT CMD
0x0
0x0
BERR
XXX
XXX
’NOT READY’
NEXT CMD
1
0
30-35