MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 390

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow
control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause
(TCR[TFC_PAUSE]), the transmitter sets TCR[GTS] internally. When the transmission of data
frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts. Following EIR[GRA]
assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control
pause (TCR[TFC_PAUSE]) and TCR[GTS] are cleared internally.
The user must specify the desired pause duration in the OPD register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection,
transmit flow control pause (TCR[TFC_PAUSE]) still may be asserted and will cause the
transmission of a single pause frame. In this case, the EIR[GRA] interrupt will not be asserted.
19.3.11 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After
completing a transmission or after the backoff algorithm completes, the transmitter waits for
carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may
begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier
sense asserts during the last 36 bit times, it will be ignored and a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an
inter-packet gap between receive frames is less than 28 bit times, the following frame may be
discarded by the receiver.
19.3.12 Collision Handling
If a collision occurs during frame transmission, the Ethernet controller will continue the
transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the
collision occurs during the preamble sequence, the JAM pattern will be sent after the end of the
preamble sequence.
If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a
random number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times,
then no retransmission is performed and the end of frame buffer is closed with a Late Collision
(LC) error indication.
19.3.13 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode,
both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal
and external loopback are configured using combinations of the LOOP and DRT bits in the RCR
register and the FDEN bit in the TCR register.
For both internal and external loopback set FDEN = 1.
MCF5271 Reference Manual, Rev. 2
19-46
Freescale Semiconductor