MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 168

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Power Management
8.3
The functions and characteristics of the low-power modes, and how each module is affected by, or
affects these modes are discussed in this section.
8.3.1
The system enters a low-power mode by executing a STOP instruction. Which mode the device
actually enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD].
Entry into any of these modes idles the CPU with no cycles active, powers down the system and
stops all internal clocks appropriately. During stop mode, the system clock is stopped low.
For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is
issued.
A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events
consist of any of these conditions:
Exiting from low power mode via an interrupt request requires:
8-4
• Any type of reset
• Any valid, enabled interrupt request
Bits
7–6
5–4
2–0
3
Functional Description
Low-Power Modes
STPMD
Name
LPMD
—
—
Low-power mode select. Used to select the low-power mode the chip enters once the
ColdFire CPU executes the STOP instruction. These bits must be written prior to
instruction execution for them to take effect. The LPMD[1:0] bits are readable and writable
in all modes. Below illustrates the four different power modes that can be configured with
the LPMD bit field.
Note: If LPCR[LPMD] is cleared, then the MCF5271 will stop executing code upon issue
of a STOP instruction. However, no clocks will be disabled.
Reserved, should be cleared.
CLKOUT stop mode. Controls CLKOUT operation during stop mode.
0 CLKOUT enabled during stop mode.
1 CLKOUT disabled during stop mode.
Reserved, should be cleared.
Table 8-4. LPCR Field Descriptions
MCF5271 Reference Manual, Rev. 2
LPMD[1:0]
10
01
00
11
Description
STOP
DOZE
Mode
WAIT
RUN
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