MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 457

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

24.4.1.2.2 External Clock
An external source clock (DTnIN) can be used as is or divided by 16.
If f
24.4.2
Figure 24-18
and operating registers, which are described generally in the following sections and described in
detail in
24.4.2.1 Transmitter
The transmitter is enabled through the UART command register (UCRn). When it is ready to
accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data from the
CPU to a serial bit stream on UnTXD. It automatically sends a start bit followed by the
programmed number of data bits, an optional parity bit, and the programmed number of stop bits.
The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock
source.
Freescale Semiconductor
extc
Transmit Buffer
is the external clock frequency, then the baud rate can be described with this equation:
(2 Registers)
Section 24.3, “Memory Map/Register
(UTBn)
Transmitter and Receiver Operating Modes
UART
is a functional block diagram of the transmitter and receiver showing the command
Figure 24-18. Transmitter and Receiver Functional Diagram
UART Receive
Buffer (URBn)
(4 Registers)
Receiver Holding Register 1
UART Command Register (UCRn)
UART Mode Register 1 (UMR1n)
UART Mode Register 2 (UMR2n)
UART Status Register (USRn)
Transmitter Holding Register
Receiver Holding Register 2
MCF5271 Reference Manual, Rev. 2
Transmitter Shift Register
Receiver Holding Register 3
UARTn
Baudrate
Receiver Shift Register
Definition.”
=
-------------------- -
(16 or 1)
f
extc
R/W
R/W
R
W
W
R
FIFO
Functional Description
Interface
External
UnRXD
UnTXD
24-19