MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 600

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Base Address: IPSBAR
Base Address: IPSBAR
0x00_0040
0x00_0044
0x00_0048
0x00_004C
0x00_0050
0x00_0054
0x00_0080
0x00_0084
0x00_0088
0x00_008C
0x00_0090
0x00_0094
0x00_0098
0x00_009C
0x00_00A0
0x00_00A4
0x00_00A8
0x00_00AC
0x00_00B0
0x00_00B4
0x00_00B8
Offset
Offset
Page
Page
18-5
18-6
18-9
18-6
18-9
16-7
16-8
16-9
16-7
16-8
16-9
16-7
16-8
16-9
16-7
16-8
16-9
16-7
16-8
16-9
—
DRAM Address and Control Register 0
DRAM Address and Control Register 1
Chip Select Address Register—Bank 0
Chip Select Address Register—Bank 1
Chip Select Address Register—Bank 2
Chip Select Address Register—Bank 3
Chip Select Address Register—Bank 4
Chip Select Control Register—Bank 0
Chip Select Control Register—Bank 1
Chip Select Control Register—Bank 2
Chip Select Control Register—Bank 3
Chip Select Control Register—Bank 4
Chip Select Mask Register—Bank 0
Chip Select Mask Register—Bank 1
Chip Select Mask Register—Bank 2
Chip Select Mask Register—Bank 3
Chip Select Mask Register—Bank 4
DRAM Mask Register block 0
DRAM Mask Register block 1
DRAM Control Register
Register Description
Register Description
Table A-5. EIM (Chip Selects) Memory Map
Table A-4. SDRAMC Memory Map
[31:24]
[31:24]
CSAR0
CSAR1
CSAR2
CSAR3
CSAR4
DCR
[23:16]
[23:16]
DACR0
DACR1
CSMR0
CSMR1
CSMR2
CSMR3
CSMR4
DMR0
DMR1
[15:8]
[15:8]
CSCR0
CSCR1
CSCR2
CSCR3
CSCR4
[7:0]
[7:0]