MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 86

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
If the operand alignment fails these guidelines, it is misaligned. The processor core decomposes
the misaligned operand reference into a series of aligned accesses as shown in
3.8.2
The execution times for the MOVE.{B,W} instructions are shown in
provides the timing for MOVE.L.
For all tables in this section, the execution time of any instruction using the PC-relative effective
addressing modes is the same for the comparable An-relative mode.
The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.
3-20
3. The OEP completes all memory accesses without any stall conditions caused by the
4. All operand data accesses are aligned on the same byte boundary as the operand size: that
(d
(d
Source
(xxx).w
8
(An)+
-(An)
memory itself. Thus, the timing details provided in this section assume that an infinite
zero-wait state memory is attached to the processor core.
is, 16 bit operands aligned on 0-modulo-2 addresses and 32 bit operands aligned on
0-modulo-4 addresses.
(An)
16
,An,Xi)
Dn
An
,An)
MOVE Instruction Execution Times
1(0/0)
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
Rx
Table 3-13. Move Byte and Word Execution Times
Address[1:0]
Table 3-12. Misaligned Operand References
X1
X1
10
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
(Ax)
MCF5271 Reference Manual, Rev. 2
Word
Long
Long
Size
(Ax)+
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
Operations
Word, Word
Byte, Word,
Byte, Byte
Destination
Kbus
Byte
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
-(Ax)
1(0/1) if write
2(0/2) if write
1(0/1) if write
2(1/0) if read
3(2/0) if read
2(1/0) if read
(d
Additional
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
C(R/W)
16
—
—
,Ax)
Table
(d
3-13, while
8
2(0/1)
2(0/1)
4(1/1)
4(1/1)
4(1/1)
,Ax,Xi)
—
—
—
Freescale Semiconductor
Table
3-12.
(xxx).wl
Table 3-14
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
—
—
—