MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 173

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

8.3.2.12 Fast Ethernet Controller (FEC)
In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes.
In stop mode, the FEC stops immediately and freezes operation, register values, state machines,
and external pins. During this mode, the FEC clocks are shut down. Coming out of stop mode
returns the FEC to operation from the state prior to the low-power mode entry.
8.3.2.13 I/O Ports
The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power
current draw if they are configured as outputs and are sourcing current to an external load. If
low-power mode is exited by a reset, the state of the I/O pins will revert to their default direction
settings.
8.3.2.14 Reset Controller
A power-on reset (POR) will always cause a chip reset and exit from any low-power mode.
In wait and doze modes, asserting the external RESET pin for at least four clocks will cause an
external reset that will reset the chip and exit any low-power modes.
In stop mode, the RESET pin synchronization is disabled and asserting the external RESET pin
will asynchronously generate an internal reset and exit any low-power modes. Registers will lose
current values and must be reconfigured from reset state if needed.
If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE)
bits in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the
chip and exit any low-power modes.
If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout
may generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.
8.3.2.15 Chip Configuration Module
The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode
is exited by a reset, chip configuration may be executed if configured to do so.
Freescale Semiconductor
• Clearing the ECNTRL[ETHER_EN] bit disables the FEC function.
• The FEC is unaffected by wait mode and may generate an interrupt to exit this mode.
MCF5271 Reference Manual, Rev. 2
Functional Description
8-9