MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 618

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Instructions
Interrupt controller
J
JTAG
Index-4
slave mode 25-16
additions 3-9
enhancements
execution timing
JTAG
PULSE 30-3
RTE 3-15
interrupts
memory map 13-4
operation
overview 13-1
registers
instructions
address (I2ADR) 25-8
control (I2CR) 25-10
data I/O (I2DR) 25-12
frequency divider (I2FDR) 25-9
status (I2SR) 25-11
BITREV 3-27
BYTEREV 3-28
FF1 3-29
STRLDSR 3-30
branch 3-26
EMAC 3-25
miscellaneous 3-24
MOVE 3-20
one-operand 3-21
two-operand 3-22
BYPASS 29-10
CLAMP 29-10
ENABLE_TEST_CTRL 29-10
EXTEST 29-9
HIGHZ 29-10
IDCODE 29-9
SAMPLE/PRELOAD 29-9
debug 3-15
PIT 21-7
prioritization 13-3
recognition 13-3
sources 13-13
vector determination 13-4
low-power modes 8-8
(IACKLPRn) 13-11
interrupt control (ICRnx) 13-12
interrupt force high/low (INTFRCHn,
interrupt pending high/low (IPRHn, IPRLn) 13-6
interrupt request level (IRLRn) 13-11
mask high/low (IMRHn, n) 13-7
INTFRCLn) 13-9
–
13-2
,
1-8
MCF5271 Reference Manual, Rev. 2
L
Low-power modes
low-power modes 8-11
memory map 29-5
nonscan chain operation 29-11
registers
signals
TAP controller 29-7
doze 8-5
peripheral behavior
run 8-5
stop 8-5
summary 8-11
BYPASS 29-10
CLAMP 29-10
ENABLE_TEST_CTRL 29-10
EXTEST 29-9
HIGHZ 29-10
IDCODE 29-9
SAMPLE/PRELOAD 29-9
bypass 29-6
IDCODE 29-5
instruction shift (IR) 29-5
TEST_CTRL 29-6
JTAG_EN 29-3
TCLK 29-4
test data input/development serial input
test data output/development serial output
test reset/development serial clock
CCM 8-9
chip select module 8-7
clock module 8-10
core 8-6
debug 8-10
DMA controller 8-7
DTIM 8-8
EPORT 8-10
Ethernet 8-9
GPIO 8-9
I
interrupt controller 8-8
JTAG 8-11
modules 8-7
PIT 8-10
QSPI 8-8
reset controller 8-9
SCM 8-6
SDRAM controller 8-6
SRAM 8-6
WDT 8-10
2
C 8-7
(TDI/DSI) 29-4
(TDO/DSO) 29-5
(TRST/DSCLK) 29-4
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