MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 584

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
The BDM programming model supports reads and writes to the A7 and other_A7 registers
directly. It is the responsibility of the external development system to determine the mapping of
the two hardware registers (A7, other_A7) to the two program-visible definitions (supervisor and
user stack pointers), based on the Supervisor bit of the status register.
BDM Accesses of the EMAC Registers
The presence of rounding logic in the output datapath of the EMAC requires that special care be
taken during any BDM-initiated reads and writes of its programming model. In particular, it is
necessary that any result rounding modes be disabled during the read/write process so the exact
bit-wise contents of the EMAC registers are accessed.
As an example, any BDM read of an accumulator register (ACCn) must be preceded by two
commands accessing the MAC status register. Specifically, the following BDM sequence is
required:
BdmReadACCn (
)
Likewise, the following BDM sequence is needed to write an accumulator register:
BdmWriteACCn (
)
Additionally, it is required that writes to the accumulator extension registers be performed after
the corresponding accumulators are updated. This is needed since a write to any accumulator alters
the contents of the corresponding extension register.
For more information on saving and restoring the complete EMAC programming model, see
Section 4.4.1.1.2, “Saving and Restoring the EMAC Programming
30.5.3.3.10Write Control Register (
The operand (longword) data is written to the specified control register. The write alters all 32
register bits.
30-34
rcreg
wcreg
rcreg
wcreg
rcreg
wcreg
wcreg
wcreg
macsr;
#0,macsr;
accn;
#saved_data,macsr;// restore the original macsr
macsr;
#0,macsr;
#data,accn;
#saved_data,macsr;// restore the original macsr
MCF5271 Reference Manual, Rev. 2
// read macsr contents & save
// disable all rounding modes
// read the desired accumulator
// read macsr contents & save
// disable all rounding modes
// write the desired accumulator
WCREG
)
Model.”
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