MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 602

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Base Address:
UART0: IPSBAR + 0x00_0200
UART1: IPSBAR + 0x00_0240
UART2: IPSBAR + 0x00_0280
1
2
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation
is not disabled, undesirable results may occur.
This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or reception of characters.
Register contents may also be changed.
Offset
0x0C
0x1C
0x3C
0x00
0x04
0x08
0x10
0x14
0x18
0x34
0x38
24-10
24-10
24-12
24-12
24-13
24-13
24-14
24-14
24-15
24-15
24-16
24-16
24-16
Page
24-5
24-7
24-8
(Write) UART Output Port Bit Reset Command Register
(Write) UART Output Port Bit Set Command Register
(Read) UART Input Port change Register
(Write) UART Auxiliary Control Register
(Read) UART Interrupt Status Register
(Write) UART Interrupt Mask Register
(Write) UART Clock Select Register
(UART/Write) UART transmit buffer
(UART/Read) UART receive buffer
(Write) UART Command Register
(Read) UART Input Port Register
(Read) UART Status Register
UART Divider Upper Register
UART Divider Lower Register
UART Mode Registers
(Read) Do not access
(Read) Do not access
(Read) Do not access
(Write) Do not access
(Read) Do not access
(Read) Do not access
Register Description
Table A-7. UART Memory Map
2
2
2
2
2
2
1
1
1
UIPCRn
UMR1n
UMR2n
UCSRn
UACRn
[31:24]
UBG1n
UBG2n
UOP1n
UOP0n
UIMRn
UISRn
USRn
UCRn
URBn
UTBn
UIPn
[23:16]
[15:8]
[7:0]